1. Field of the Invention
The invention relates to the process of designing an integrated circuit. More specifically, the invention relates to a method and an apparatus for modifying a hierarchical representation of a circuit in order to efficiently analyze features created by interactions between cells in the hierarchical representation.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process generally begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term xe2x80x9cmaskxe2x80x9d as used in this specification is meant to include the term xe2x80x9creticle.xe2x80x9d) Exposure energy is then shone on the mask from an exposure energy source, such as a visible light source or an ultraviolet light source.
This exposure energy is generally reduced and focused through an optical system that contains a number of lenses, filters and mirrors. The exposure energy passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the exposure energy is blocked by opaque regions of mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
A layout for a semiconductor chip is often stored in a standard hierarchical format, such as GDSII stream format. For example, FIGS. 1A, 1B and 1C illustrate how a layout, T, can be composed of a sub-cell A and a sub-cell B, wherein the sub-cell A further includes a sub-cell C. FIG. 1A illustrates a nodal representation of this hierarchy, while FIG. 1B illustrates a corresponding graphical representation.
FIG. 1C presents a specification of the layout in code form. In this form, the layout, T, includes a reference list. This reference list includes a reference to cell A along with an associated transformation, TA, and a reference to cell B along with an associated transformation, TB. Similarly, the layout for cell A includes geometrical features associated with cell A along with a reference cell C. This reference to cell C is accompanied by a transformation of cell C with respect to A, TCA. The layouts for cell B and cell C include geometrical features associated with cell B and cell C, respectively.
Representing a layout in a hierarchical form can cause problems for various operations related to fabrication of a semiconductor chip, because interactions between nodes within the hierarchical representation can cause unintended results. These problems can be remedied by collapsing the hierarchy down into a single monolithic layout before performing the operations. Unfortunately, this can be prohibitively slow because the operations must be applied to the entire monolithic layout, even though many of the cells in the layout may be repeated.
What is needed is a method and an apparatus for performing a computational operation on a hierarchical representation of a layout without performing the computational operation over the entire layout, and without the above-described problems associated with using a hierarchical representation.
In particular, one problem arises during the generation of phase shifters. Phase shifters are often incorporated into a mask in order to achieve line widths that are smaller than the wavelength of the exposure energy that is used to expose the photoresist layer through the mask. During phase shifting, the destructive interference caused by two adjacent clear areas on a mask is used to create an unexposed area on the photoresist layer. This is accomplished by exploiting the fact that exposure energy passing through a mask""s clear regions exhibits a wave characteristic having a phase that is a function of the distance the exposure energy travels through the mask material. By placing two clear areas adjacent to each other on the mask, one of thickness t1 and the other of thickness t2, one can obtain a desired unexposed area on the underlying photoresist layer caused by interference. By varying the thickness t1 and t2 appropriately, the exposure energy exiting the material of thickness t2 is 180 degrees out of phase with the exposure energy exiting the material of thickness t1. Phase shifting is described in more detail in U.S. Pat. No. 5,858,580, entitled xe2x80x9cPhase Shifting Circuit Manufacture Method and Apparatus,xe2x80x9d by inventors Yao-Ting Wang and Yagyensh C. Pati, filed Sep. 17, 1997 and issued Jan. 12, 1999, which is hereby incorporated by reference.
For example, referring to FIG. 2A, a phase shifter is composed of a zero-degree phase clear area 254 that works in concert with a 180-degree phase clear area 258 to reduce the width of polysilicon line 256 in the gate region of a transistor 250. This first transistor selectively creates a conducting path between diffusion region 252 and diffusion region 260.
Note that a thin chromium regulator 255 can be added to the mask between zero-degree phase clear area 254 and 180-degree phase clear area 258 in order to better control gate width.
The phase shifter is typically incorporated into a separate phase shifting mask, which is used to reduce the width of polysilicon line 256 in the gate region of transistor 250.
Phase shifters are typically extended past the active diffusion region of a transistor by a certain margin. For example, in FIG. 2B, the phase shifter comprised of the zero-degree phase region 204 and 180-degree phase region 206 is extended past the endcap of the transistor by an endcap margin 212 (for example, 200 nm). On the other side of the transistor, the phase shifter is extended past the active diffusion region by a fieldcap margin 214 (for example, 80 nm). Note that the endcap margin 212 is larger than the fieldcap margin 214 because the transistor endcap may be susceptible to line end shortening, which can be somewhat mitigated by extending the phase shifter by an additional margin.
Sizing phase shifters can be a problem in a hierarchical layout because interactions between cells may case endcaps to become fieldcaps. For example in FIG. 3A, endcap 306 in cell 302 joins with endcap 316 in cell 304 so that they are no longer endcaps. Similarly, in FIG. 3B, endcap 306 in cell 302 interacts with polysilicon region 322 in cell 320 to form a fieldcap. In both of these examples, it is desirable to know that the inter-cell interactions cause endcaps 306 and 316 to become fieldcaps in order to appropriately size the phase shifters. However, using existing techniques, this can only be accomplished by collapsing the design hierarchy so that the interactions become visible. As mentioned above, collapsing the design hierarchy can greatly increase the time required to process the layout.
Hence, what is needed is a method and an apparatus for forming phase shifters using a hierarchical representation of a layout without unnecessarily collapsing the layout.
One embodiment of the invention provides a system for analyzing a layout related to a circuit on a semiconductor chip. The system operates by receiving a design hierarchy specifying the layout of the circuit. This layout includes a set of hierarchically organized nodes, wherein a given node specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes located under the given node in the design hierarchy. The system operates by modifying the design hierarchy by examining a set of sibling nodes that are located under a parent node in the design hierarchy in order to identify a set of interacting geometrical features between the set of sibling nodes. Next, the system then moves the set of interacting geometrical features to a new child node under the parent node, and then performs an analysis on the modified design hierarchy.
In one embodiment of the invention, the system identifies other sets of sibling nodes with equivalent sets of interacting geometrical features. This allows the system to use the new child node in analyzing the other sets of sibling nodes, so that additional child nodes do not have to be recreated for the other sets of sibling nodes.
In one embodiment of the invention, while moving the set of interacting geometrical features to the new child node, the system first moves the set of interacting geometrical features from the set of sibling nodes to the parent node. Next, the system creates the new child node under the parent node, and then moves the set of interacting geometrical features from the parent node to the new child node.
In one embodiment of the invention, the system also identifies a second set of interacting geometrical features between the parent node and the set of sibling nodes. The system then moves this second set of interacting geometrical features from the parent node to the set of sibling nodes.
In one embodiment of the invention, performing the analysis involves identifying transistors and associated transistor endcaps within the circuit, wherein the set of interacting geometrical features defines at least some of the transistors and associated transistor endcaps. Next, the system generates phase shifters to be used in fabricating some of the identified transistors, wherein the layout of a given phase shifter is affected by a location of an associated endcap for the given phase shifter.
In one embodiment of the invention, the set of interacting geometrical features define diffusion regions on the semiconductor chip.
In one embodiment of the invention, the layout can define either features on the semiconductor chip, or a mask that is used to create features on the semiconductor chip.
In one embodiment of the invention, the design hierarchy is specified in GDSII format.
One embodiment of the invention provides a system for analyzing a layout related to a circuit on a semiconductor chip. The system operates by receiving a design hierarchy specifying the layout of the circuit. This design hierarchy includes a set of hierarchically organized nodes, wherein a given node in the design hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes located under the given node in the design hierarchy. The system modifies the design hierarchy by, examining a set of sibling nodes that are located under a parent node in the design hierarchy in order to identify a set of interacting geometrical features between the set of sibling nodes. The system then moves the set of interacting geometrical features from the sibling nodes to the parent node, so that the interaction is visible at the parent node. Note that other geometrical features that do not interact remain at the sibling nodes and are not moved to the parent node. The system then performs an analysis on the modified design hierarchy. This involves analyzing the set of interacting geometrical features at the parent node.
In one embodiment of the invention, the system determines at a parent node whether interactions between related sibling nodes cause transistor endcaps to become fieldcaps, and if so, moves geometrical features that caused the interactions to the parent node.
In one embodiment of the invention, the set of interacting geometrical features define polysilicon regions and diffusion regions on the semiconductor chip.